资讯

电子工程专辑3 年

从VerilogPLI到SystemVerilogDPI的演变

写过Verilog和systemverilog的人肯定都用过系统自定义的函数$display，这是预定好的，可以直接调用的功能。但是当Verilog中的task和 ...
Design-Reuse23 年

Synopsys VCS Verilog Simulator Incorporates Breakthrough Verification Capabilities

MOUNTAIN VIEW, Calif.--(BUSINESS WIRE)--Sept. 26, 2001-- Synopsys, Inc. (Nasdaq:SNPS), the technology leader for complex IC design, today announced VCS(TM) 6.0.1, the latest release of the industry's ...
Design-Reuse2 年

Hitachi Endorses Model Technology ModelSim for Verilog Simulation

PORTLAND, Ore.--(BUSINESS WIRE)--Oct. 3, 2001--Model Technology(TM), a Mentor Graphics company, today announced that the ModelSim® hardware description language (HDL) simulator has received Verilog ...
Electronic Design23 年

Verilog Simulator Adds Full-Featured Coverage Analysis And A C/C++ Interface

The latest VCS Verilog simulator from Synopsys contains built-in comprehensive coverage analysis. With it, design teams using VCS 6.0.1 can determine their verification quality before tapeout.
EDN23 年

Verilog-2001 language ready to roll

NAPA, Calif. — Implementation of the new Verilog-2001 hardware description language became practical with the IEEE's release Wednesday (Oct. 17) of documentation that describes the standard, ...
Electronic Design23 年

Testbench Automation Tool Provides Tight Links To Verilog Simulation

Faster runtime performance, real-time access to built-in Verilog simulation coverage metrics, and a unified graphical environment for waveform analysis are all promised by version 5.0 of the VERA ...
EDN4 年

Verisity upgrades Verilog linting tool

SAN MATEO, Calif. Verisity Design Inc. has released a new version of its SureLint Verilog linting tool that supports user-defined checks, better Finite State Machine and race condition checks, and ...