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This is an attempt to fine tune SOTA Large Language Models so as to generate Verilog (VHDL ...

├── .gitignore ├── LICENSE ├── README.md ├── environment.yaml ├── requirements.txt ├── data │ └── df_small.csv │ └── formatted_small_df.csv ├── preprocessing │ └── data_preprocessing.py │ └── small_df ...