Implemented in 28-nm CMOS, the proposed digital MDLL generates 2.4-GHz clock and achieves a spur of -51.4 dBc and an rms jitter of 699 fsrms while consuming 1.5 mW from 1-V supply.

This paper presents an all-digital phase-locked loop (ADPLL) for the 2.4-GHz ISM band frequency synthesis. The ADPLL is built around a digitally controlled LC oscillator. In the feedback path, a ...

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