Riviera-PRO 2008.02 supports many features of the VHDL standard draft (IEEE P1076-2007/D4.0), recently approved by Accellera. Constructs such as new data types, subprograms and operators, matching ...

The core’s functional configuration is designed by VHDL code and designed input signal (test bench) for PPI 8255, which is generated by VHDL code.

VHDL code looks odd from a software programmer’s perspective because it’s closer to the hardware and strongly typed: an 8-bit integer isn’t the same as eight wires in VHDL.